Kĩ thuật viễn thông - Truy cập bộ nhớ trực tiếp DMA

*/Chapter6Nội dung môn họcGiới thiệu chung về hệ vi xử lýBộ vi xử lý Intel 8088/8086Lập trình hợp ngữ cho 8086Tổ chức vào ra dữ liệuNgắt và xử lý ngắtTruy cập bộ nhớ trực tiếp DMACác bộ vi xử lý trên thực tế*/Chapter6Chương 6: Truy cập bộ nhớ trực tiếp DMAGiới thiệu về DMAMạch DMAC 8237A của Intel*/Chapter6Giới thiệu về DMA*/Chapter6Mạch DMAC 8237A của Intel*/Chapter6Mạch DMAC 8237A của IntelAlthough i8237A may not appear as a discrete component in recent PCs, it’s still there (integrated in chipsets, ISPC)The i8237A has four independent DMA channelsOriginal PC/XT design had one i8237A for four DMA channelsPC/AT used two i8237As to provide 7 DMA channels i8237A is programmable device and can be configured for single transfers, block transfers, Reads, Writes or Memory-to-Memory transfers */Chapter6Mạch DMAC 8237A của Inteli8237A allows byte addressing for 8-bit data transfersIn the PC/AT design, a contrived 16-bit transfer design is implemented using the i8237A i8237A uses a multiplexed address and data bus to reduce the device pin count. DB0..DB7 lines contain the data bus along with the high byte of the 16-bit address bus. An external latch is required to demultiplex the address lines*/Chapter6Mạch DMAC 8237A của Intel*/Chapter6Mạch DMAC 8237A của Intel*/Chapter6Mạch DMAC 8237A của Intel*/Chapter6How the PC uses the i8237A*/Chapter6DMA Address TrackingThe i8237A has four registers for tracking memory addresses during a DMA blockBASE ADDRESS REGISTERBASE WORD COUNT REGISTERCURRENT ADDRESS REGISTERCURRENT WORD COUNT REGISTER*/Chapter6DMA in the PC/XT*/Chapter6Cascaded i8237As in the PC/ATDMA Cascadation*/Chapter6PC/AT DMA Channel prioritiesDMA channel 0 (DREQ0) has the highest priorityDMA channel 7 (DREQ7) has the lowestNote, when a DMA transfer is in session, it cannot be 'interrupted' by another DMA request, even if the DMA request is made by a higher priority DMA channel.The current DMA transfer session will be completed before the pending DMA request is accepted */Chapter6DMA Channels in the PC/AT DMA Priority Pre-defined 8-bit or Use in PC/AT 16-bit____________________________________________________________DREQ0 Highest Memory Refresh* 8-bits DREQ1 Not defined 8-bits DREQ2 Floppy Disk 8-bits DREQ3 Not defined 8-bits DREQ4 Cascade not used DREQ5 Not defined 16-bits DREQ6 Not defined 16-bits DREQ7 Lowest Not defined 16-bits